RISC-V Memory

A RISC-V hart has a single byte-addressable address space of 2XLEN bytes for all memory accesses.

XLEN is a property that defines the data size.
A hart is a RISC-V execution context that contains a full set of RISC-V architectural registers.

A word of memory is defined as 32 bits (4 bytes).

Correspondingly,
1. A halfword is 16 bits (2 bytes),
2. A doubleword is 64 bits (8 bytes), and
3. A quadword is 128 bits (16 bytes).

The memory address space is circular so that the byte at address 2XLEN −1 is adjacent to the byte at address zero.

Accordingly, memory address computations done by the hardware ignore overflow and instead wrap around modulo 2XLEN (|2XLEN|).

The execution environment determines the mapping of hardware resources into a hart’s address space.

Different address ranges of a hart’s address space may (1) be vacant, or (2) contain main memory, or (3) contain one or more I/O devices.

Executing each RISC-V machine instruction entails one or more memory accesses, subdivided into implicit and explicit accesses.

For each instruction executed, an implicit memory read (instruction fetch) is done to obtain the encoded instruction to execute.

Many RISC-V instructions perform no further memory accesses beyond instruction fetch. Specific load and store instructions perform an explicit read or write of memory at an address determined by the instruction.

The execution environment determines what portions of the non-vacant address space are accessible for each kind of memory access.

For example, the set of locations that can be implicitly read for instruction fetch may or may not have any overlap with the set of locations that can be explicitly read by a load instruction and the set of locations that can be explicitly written by a store instruction may be only a subset of locations that can be read.

Ordinarily, if an instruction attempts to access memory at an inaccessible address, an exception is raised for the instruction. Vacant locations in the address space are never accessible.

The memory accesses (implicit or explicit) made by a hart may appear to occur in a different order as perceived by another hart or by any other agent that can access the same memory.

This perceived reordering of memory accesses is always constrained, however, by the applicable memory consistency model.

The default memory consistency model for RISC-V is the RISC-V Weak Memory Ordering (RVWMO).